Design and Performance Estimation of Delta Networks for MPSOC on Programmable Circuits

Multiprocessor systems on chip (MPSoC) designs are increasingly being used in today’s embedded system, to follow phenomenal increase of embedded products performance requirements. In these systems one of the most critical components regarding overall efficiency is on-chip interconnections which have a great impact on the performance constraints of modern MPSOC. Multistage interconnection networks have been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts in the semiconductor industry for solving the problems related to on-chip communications. This paper proposes the design and implementation of a flexible and scalable Delta network for MPSOC in an FPGA. The configurable Delta MIN provides a variety of network topologies with the convenience of a manager for configuration.